Communication between computer systems usually involves a commanding system sending a command to a commanded system. Sometimes the command causes data to be transmitted either from the commanding system to the commanded system (a write operation) or from the commanded system to the commanding system (a read operation). Whether any data is transmitted or not, the commanded system always sends a response back to the commanding system that describes the ending state of the command.
In prior systems, any central processor (CPU) or support auxiliary processor (SAP) in the system (CPC) sent command signals to its intersystem channel to send a message to another processor coupled to the commanding system. The intersystem channel in turn did processing operations for the command, including sending the command over a channel link to a coupling facility (CF). The CF contains a processor for processing received frames of control information and optional data information it receives from or transmits to the CPC. After the commanded system (e.g. CF) processes the command (and receives/sends any data associated with the command), it sends a response back to the commanding system (e.g. CPC) to indicate the status of the receiving system in regard to its command operations. When the response status signals (response) are received at the commanding system, the CPU sending the command handles the response. The accepting CPU's instruction stream in the CPC must be interrupted for that CPU to handle the response. When interrupted, the accepting CPU then sends another command to the intersystem channel instructing it on where and how to store the received response into a communication area in the commanding systems main memory (i.e. CPC shared storage), and these operations take a significant amount of time. Sometimes commands and/or responses need to be retransmitted due to failures in the initial transmissions; and any such retransmission of a command and/or response has involved similar acceptance and interruption overhead by a CPU which accepts the burden of being interrupted to handle the retransmission of the response from the CF.
Delay is introduced in the overall execution of commands by the central processors when they are interrupted (or polled) for acceptance and handling of a response received by an intersystem channel. A significant amount of potential processor power is consumed in accepting, waiting, processing and moving a response between a CPC's intersystem storage and the CPC's main memory.